Specialist Polyimide Polymers

Solutions for Critical and Demanding Applications

Bringing together high purity, plasma resistance and dimensional stability without outgassing, even in an ultra-hard vacuum.

Plasma Etching

Plasma etch processes in advanced semiconductor manufacturing are characterised by high-energy ions, electrons and neutral particles bombarding the wafer surface to create appropriate trenches and doping zones. A range of high-purity molecules to generate the plasma allows specific etching characteristics such as anisotropy.

While etching processes occur in a lower vacuum level (typically 10-4 – 10-5 bar) than deposition processes, the plasma bombardment uses higher energies, offsetting this simplification.

Plasma chamber furniture must resist high-energy plasma at the employed temperature and energy levels to be a useful solution in advanced semiconductor manufacturing processes. Any small amount of material lost should not contain metallic or other conductive particles, as these can fatally impair the functioning of the individual components on the wafer. The plasma chamber furniture’s high purity (i.e., freedom from metallic impurities) is an essential contributor to the yield of viable devices from advanced semiconductor manufacturing.

As some components used in the plasma chamber, for example, electrostatic chucks, can contain metallic components as electrical conductors embedded deep within the chuck, the materials used for the manufacture of such a chuck must be either well-matched to the metallic in terms of thermal expansion or are sufficiently tough and elastic to accommodate any resultant mismatch over the intended temperature range.

Temperatures in a plasma etching chamber are generally elevated and can increase further during etching operations. Materials selected for furniture in plasma chambers must withstand these temperatures without outgassing volatiles, which can add to the overall burden of contamination experienced by the wafer. Like other vacuum processes, water outgassing is undesirable as it increases plasma chamber pump-down times.

Ducoya can be very useful in plasma etch environments due to its resistance to many plasma species, including halogen or halogenated species that can be particularly aggressive to aluminium nitride (AlN) and silicon dioxide-based ceramics. While Ducoya is not indestructible, it has very low particle generation in high-energy plasma. Duvelco’s patent-pending manufacturing process uses novel solvents, producing an exceptionally pure material. Even when erosion does occur, it does not significantly contribute to a loss in yield through particulate or metallic ion contamination.

Ducoya is “soft but strong”, meaning it can effectively contact or hold a wafer securely without damage or high local stress levels. However, this does not imply that Ducoya is not strong and tough. Ducoya is highly resistant to mechanical damage and can withstand significant force without being damaged easily. A high level of elastic recovery can usefully accommodate a thermal expansion mismatch between contacting materials without building excessive stress or cracking. This high level of durability and accommodation can be exciting for those experienced in the performance of ceramics and looking for more robust components compatible with the harsh environment.

Ducoya can operate at high temperatures with minimal outgassing, even in the vacuum environment of semiconductor operations. In a vacuum, continuous temperatures of greater than 400°C are possible. Ducoya exhibits no phase transitions or Tg (glass transition) from close to absolute zero to >400°C. Its mechanical behaviour is consistent, especially regarding thermal expansion and related dimensional stability. Ducoya can also be machined to tight tolerances and high levels of surface finish. Low levels of water absorption help minimise chamber pump-down times, contributing to increased productivity.

If you are interested in more information on the interesting features of Ducoya and its use in semiconductor manufacturing applications, see our applications guide.

Wafer Handling and Die Transport

A characteristic of semiconductor manufacturing is moving wafers from one process step to the next repeatedly. Wafers are fragile and sensitive to mechanical and electrostatic damage and contamination with impurities. They can be at elevated temperatures and come in sizes ranging from 100mm to 450mm in diameter.

Wafers that have undergone back grinding before dicing can be particularly fragile in a mechanical sense due to their slender thickness. This state continues prior to mounting on a Wafer Support System (WSS). There is also a requirement to accommodate warped wafers.

Equipment manufacturers employ various systems to transport wafers around foundries and fabs. These include vacuum, simple air pressure, the Bernoulli effect, mechanical lifting pins and edge grips. End effectors are commonly used with a variety of these techniques to lift wafers from the processes and place them into containment boxes that may be Front Opening Universal Pods (FOUPS), Standard Mechanical Interfaces (SMIFs), Front Opening Shipping Boxes (FOSBs) or Open Cassettes. In some semiconductor processes, such as LCD manufacturing, balls may facilitate the movement of large LCD panels.

After dicing and possibly ‘binning’, individual dies must be transported to and through the back-end test process. Until final packaging is complete, dies remain sensitive to mechanical and electrostatic damage and contamination with impurities. Post-test, there is an additional complication of identifying and tracking chips if they have been ‘binned’ at different performance levels.

Wafer guides can help get the wafer to where it needs to be, but these need to be wear-resistant to avoid generating particles and potentially contaminating the wafer. Of course, parts that wear quickly give a short lifetime, which can also be undesirable in any environment, but particularly in a clean room environment where every unscheduled operation carries contamination risks.

Any transport system must, therefore, be able to facilitate the movement of these fragile semiconductor components without inflicting damage or degradation on their high-value componentry.

Ducoya addresses these challenges in several ways. Extreme purity reduces the possibility of contamination through intended contact (as in the case of pick-up tips, also known as vacuum tips) or unintended contact, for example, in the case of Bernoulli effect end effectors, where a process hiccup causes a ‘touch down’ (or ‘touch up’).

Ducoya is also ‘soft but strong’, allowing a soft contact in vacuum operations and mechanical edge contact while also being strong enough not to deform even at high temperatures. Ducoya can be machined to tight tolerances, which can be necessary for the finely defined dynamics of Bernoulli operations or vacuum tips to ensure good performance with minimum use of air or vacuum.

Ducoya G021 dissipates electrostatic charges, helping to reduce the chance of electrostatic damage. Due to their wear-resistant nature, Ducoya parts maintain their performance over long periods of frequent use. This lack of wear, coupled with high purity, also reduces the generation of particulates that may contaminate other surfaces or wafers.

If you are interested in more information on the interesting features of Ducoya and its use in semiconductor manufacturing applications, see our applications guide.

Plasma Enhanced Deposition

In semiconductor manufacturing, plasma-enhanced deposition processes can only deliver high yields in a hard vacuum, 10-9 bar not being uncommon; even space has more molecules per cubic metre than the chambers used for advanced plasma-enhanced deposition processes, such as Plasma-Enhanced Chemical Vapour Deposition (PECVD) and Plasma Enhanced Atomic Layer Deposition (PEALD).

Even a tiny particle landing in an inopportune location on a wafer can be enough to scrap that particular device; particle generation, especially of conductive ions, is undesirable to achieve acceptable yields.

Outgassing is similarly undesirable. Outgassed volatiles add to the impurity burden in the chamber, which can result in defective devices. All outgassing adds to the time taken to achieve operating levels of vacuum, which can lower productivity in a competitive market. Buyers of advanced semiconductor manufacturing equipment that can cost hundreds of millions of dollars need excellent productivity to help generate returns on this substantial investment.

Ducoya can help the productivity and yield of advanced semiconductor devices through excellent plasma resistance, which means a low erosion rate. Coupled with exceptionally high purity, it means minimal conductive particles or metallic ions.

Ducoya also has low water absorption, and what there is can be removed by drying in a conventional or vacuum oven before component use.

The Ducoya molecule has high bond energies and intermolecular attraction, as shown by its impressive maximum continuous use temperature greater than 400°C in a vacuum. This high-energy combination, coupled with high purity, keeps volatile outgassing to negligible levels even in the hardest vacuums demanded by modern plasma-enhanced deposition equipment.

If you are interested in more information on the interesting features of Ducoya and its uses in semiconductor manufacturing applications, see our applications guide.

Back-end Test

Test sockets perform a vital function towards the end of the semiconductor manufacturing process. A “die” is a term used to describe many integrated circuits, such as an application-specific integrated circuit (ASIC) and micro-electrical mechanical systems (MEMS). Each Integrated Circuit (IC) is tested up to 20 times to ensure robust behaviour. For a fab producing millions or billions of ICs for testing yearly, test sockets are subject to a significant amount of wear.

The test socket must also account for small-scale misalignment between pins and socket, gently guiding the die into place on the test socket and making good electrical connections rapidly. Naturally, this sequence cannot damage or deform the IC (die).

As pin counts per unit size on advanced semiconductors have increased, so has the complexity of producing reliable and accurate test sockets. Numerous electrical connections need to be made and broken quickly for each IC. None of the constant insertion and removal can affect the IC’s responses to the tested function, whether that be high-frequency signals, high voltages, the intended MEMS functionality, or something else. Of course, all of these measurements can be combined and permutated. Consistency and accuracy of results, therefore, absolutely depend on the wear resistance of the test socket material.

The excellent electrical properties of any test socket are fundamental to producing consistent and predictable results, meaning consistent and high resistive values over a range of temperatures.

Ducoya has exceptional wear resistance, a defining attribute of many Ducoya applications. Ducoya is also conformal but strong; at Duvelco, we sometimes refer to “soft but strong” as a characteristic. In the context of back-end test sockets, this means guiding the pins to a good electrical connection without damage.

Ducoya can be machined to extremely tight tolerances and is dimensionally stable with very low moisture absorption and consistent and predictable changes concerning temperature. Ducoya does not have phase transitions or exhibit a Tg (glass transition).

Ducoya G001 is an excellent electrical insulator with resistance values over 1015 Ω. Ducoya also has a high dielectric strength and a low dielectric k value for high test frequencies.

If you are interested in more information on the interesting features of Ducoya and its use in semiconductor manufacturing applications, see our applications guide.


Once the wafer is complete and individual ICs have been tested and perhaps ‘binned’ (sorted into performance categories), there are two mechanical steps before moving entirely into back-end test and packaging.

One of these steps is backgrinding; the other is dicing. These steps could be completed in either order today, although the historical practice was to backgrind the wafer and then dice it. However, both approaches are in use today. Backgrinding the wafer has the advantage of completing the operation in a single step, but it leaves the wafer more fragile at the end of the process, which may need additional support. Backgrinding individual ICs (or dies) has the advantage of leaving a smaller and mechanically more robust die. During backgrinding, keeping track of any binning that may have occurred is important.

For the dicing operation itself, the objective is to cut the wafer cleanly without damaging any of the dies on the wafer. Dicing lanes are provided to separate individual components and allow some room for ‘kerf’ (material removed and therefore lost by a cutting process) and tolerances.

There are presently three primary techniques used for dicing wafers:

Mechanical dicing

The most established is mechanical dicing, a.k.a. blade dicing using metallic wheels with diamonds or cubic boron nitride (CBN) abrasives bonded to the thin metallic wheels. These cutting discs rotate at high speed (perhaps 30,000 rpm) and physically remove silicon and other wafer layers to create individual dies. Cuts in two directions are required, typically sequentially. Thus, a 300mm wafer with a small component die may need many cuts to achieve completion. Each successfully cut dicing lane is known as a street.

Mechanical cutting is inexpensive but can physically damage the dies due to flaking, chipping or shattering (cracking) of the wafer. The cutting process can also generate heat, which may damage the die or cause warping in the wafer, making subsequent cuts more difficult. Vibration of the wafer induced by cutting through can disadvantage the physical components on MEMs chips.

Lastly, metallics from the wheel or disc that the abrasive diamonds or CBN are bonded to can contaminate the wafer and inhibit or prevent proper device functioning. These types of damage typically result in lower first-quality yields. Metallic contamination and mechanical damage can also invalidate previous test probe results, which may result in inappropriate binning.

Plasma dicing

Plasma dicing is a more recently introduced technique, using the ability of plasma to remove material for wafers selectively, including forming deep trenches, effectively dicing the wafer. The advantages claimed for plasma include minimal or no damage to the wafer and being able to dice at higher speeds as equipment is available to plasma etch (cut) multiple dicing lanes simultaneously (sometimes referred to as ‘dicing in parallel’).

Plasma dicing can also have the advantage of not generating significant heat on the wafer, avoiding distortions, which is especially useful in thin, more easily warped wafers. It is possible for plasma dicing to achieve smaller cutline widths than the typical spot size found in laser dicing. (Laser spot sizes are often c. 10µm. in this application at the time of writing).

Lastly, plasma dicing does not induce vibration. However, a check is required to ensure any manufactured MEMs chips are compatible with the (typically fluorine-based) plasma.

Plasma dicing also has some disadvantages regarding equipment cost, the need to manage gaseous extraction of vapourised material and spent plasma gas, and the requirement to achieve a reasonable level of vacuum to facilitate good and ‘fine’ control of the plasma. When transporting wafers and holding them to tight tolerances, investing in chamber furniture compatible with vacuum and plasma conditions is necessary. The furniture must be manufactured with tight tolerances to follow dicing lanes accurately.

An individual plasma pass is also typically slower than a single laser pass. Before dicing, additional time is spent in setting up a modest vacuum. This vacuum step is not required in laser or mechanical dicing. Depending on the number of lanes to be diced, either process may be faster, with smaller components and larger wafers favouring plasma (Higher component density). In contrast, larger dies on smaller wafers favour laser dicing.

Laser dicing

Laser dicing uses a high-power, high-density laser, typically a YAG (Yttrium Aluminium Garnett) laser, which lases at 1064nm in the infrared region of the electromagnetic spectrum. This is close to dual absorption lines of silicon at 1193 and 1194nm. Laser dicing works by this highly concentrated energy ablating silicon, removing material in the dicing lane and giving separated streets.

Laser dicing has the advantages of being non-contacting and does not introduce vibration. Laser cutting speeds can be high.

Laser dicing does, however, generate localised heat, which may lead to wafer warping. Ablated material can be more particulate than material moved by plasma, which tends to be more atomic. This additional particulate matter could lead to contamination of the wafer and a lower yield.

Laser dicing is the most commonly employed technique in 300mm advanced semiconductor manufacturing, while plasma dicing is the most emergent technology.

How can Ducoya® benefit my dicing process?

Mechanical dicing
Ducoya is a lightweight, high-strength bonding material for abrasives such as diamond and CBN. Ducoya has a soft but strong hold on these abrasive particles; soft enough to expose the abrasive without ‘clogging’ but strong enough to hold the abrasive particles tightly to give a long life to the cutting wheel. Ducoya also has excellent damping properties, which can minimise vibration during dicing operations, leading to higher yields.
Plasma dicing
Ducoya demonstrates excellent behaviours in a plasma environment. See plasma etching for further information. Ducoya can be helpful in chamber furniture, which is plasma resistant, has high purity to avoid contamination through contact, and is capable of being manufactured to precise tolerances for accurate positioning of the wafer. Ducoya also has low water absorption and no volatile outgassing, minimising plasma chamber pump-down times.
Laser dicing
Laser applications of Ducoya are emergent rather than established. We want to dialogue with OEMs developing any new or improved aspect of this technology to see if Ducoya can add value to the process due to Ducoya’s wide range of interesting and combinable features.

If you are interested in more information on the interesting features of Ducoya and its use in semiconductor manufacturing applications, see our applications guide.

Semiconductor Manufacturing Applications

The rate of technological evolution in the semiconductor manufacturing industry may be the fastest of all industries. In the 50 years of semiconductor devices being available to the public at scale, on-wafer feature sizes have decreased; from low microns in size to low nanometres, with a commensurate increase in component density. Semiconductor manufacturing equipment has, of course, made all this possible by evolving at a similar breakneck rate; akin to Moore’s Law.

The latest equipment brings demanding requirements on materials: high purity, plasma resistance and dimensional stability without outgassing even in an ultra-hard vacuum. For semiconductor wafer fabrication and testing, this combination of properties can result in better yields due to lower defects, shorter chamber evacuation times and longer part life. Together, these result in better utilisation of equipment for customers and increased productivity in the semiconductor market.

Lightweight, high temperature stability and chemical resistance are the properties possessed by polyimide materials that make them ideal for use in electronics applications.

Ducoya® polyimide is an excellent insulating material, widely used in electronics and electrical engineering applications from low voltage microelectronics up to high voltage engineering industry.

Common uses include test sockets and wafer guides, chosen for their excellent electrical and mechanical properties, plasma resistance, low outgassing and high oxidative stability in electronic testing and wafer handling applications.